Three-dimensional memory device and fabrication method
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsJiandong WANG, Junyang XU, Sheng XIA, Wenbin SUN, Xiaofen ZHENG, Yuping XIA
Life of this patent
Estimating the term…
Abstract
A 3D memory device includes a conductor/insulator stack, a region of memory cells in the conductor/insulator stack, and a gate line slit (GLS) structure extending along a direction. The GLS structure includes a first section, a second section, and a third section. The second section is between the first and third sections. The width of the second section is larger than the widths of the first and third sections.
Claims20
A three-dimensional (3D) memory device, comprising:
- a conductor/insulator stack including a conductive layer and a first dielectric layer alternatingly stacked;
- a region of memory cells in the conductor/insulator stack;
- and
- a gate line slit (GLS) structure extending along a first direction, the GLS structure including a first section adjacent to the region of memory cells, a second region adjacent to the first section, and a third section adjacent to the second section, the second section being between the first and third sections, a width of the second section being larger than a width of the first section and a width of the third section along a second direction, respectively, and the second direction being perpendicular to the first direction.
A three-dimensional (3D) memory device, comprising:
- a conductor/insulator stack including a conductive layer and a first dielectric layer alternatingly stacked;
- a region of memory cells in the conductor/insulator stack;
- and
- a gate line slit (GLS) structure extending along a first direction, the GLS structure including a first section adjacent to the region of memory cells and a second section adjacent to and aligned with the first section, a length of the second section being substantially shorter than a length of the first section along the first direction.
A method for fabricating a three-dimensional (3D) memory device, comprising:
- forming a dielectric stack, the dielectric stack including a first dielectric layer and a second dielectric layer alternately stacked;
- forming a channel hole structure extending through the dielectric stack along a first direction perpendicular to the first and second dielectric layers;
- and
- forming a first opening and a second opening separated from and adjacent to the first opening for a first section and a second section of a gate line slit (GLS) structure, respectively, the first and second openings extending through the dielectric stack along the first direction and extending along a second direction that is parallel to the first and second dielectric layers, and a length of the second opening being substantially shorter than a length of the first opening along the second direction.
Dependencies are inferred from the claim text.