US 2024/0206160 A1 · SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR MEMORY DEVICE

Abstract

Provided is a method of fabricating the semiconductor memory device. A stack layer, which includes sacrificial layers and first insulating interlayers alternately stacked, is formed. The sacrificial layers are positioned at an uppermost layer of the stack layer. A plurality of channel holes are formed through the stack layer. A first channel pillar is formed in each of the channel holes. A mold layer is formed on the stack layer with the first channel pillar. The mold layer includes a mold hole configured to partially expose the first channel pillar. A second channel pillar is formed in the mold hole. The mold layer and the sacrificial layer at the uppermost layer of the stack layer are then removed.

Claims12

Dependent claims

A method of manufacturing a semiconductor memory device, the method comprising:

forming a stack layer including sacrificial layers and first insulating interlayers alternately stacked, the sacrificial layer positioned at an uppermost layer of the stack layer;
forming a plurality of channel holes through the stack layer;
forming a first channel pillar in the channel holes;
forming a mold layer on the stack layer with the first channel pillar, the mold layer including a mold hole configured to partially expose the first channel pillar;
forming a second channel pillar in the mold hole;
and
removing the mold layer and the uppermost sacrificial layer.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/594,365Filed 4 Mar 2024

Priority

KR 10-2020-012019518 Sep 2020

Published

20 Jun 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 43/10
EEPROM devices comprising charge-trapping gate insulators: characterised by the top-view layout
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels

Semiconductor memory device and method of fabricating the semiconductor memory device

Life of this patent

Semiconductor memory device and method of fabricating the semiconductor memory device

Life of this patent

Abstract

Claims12