US 2024/0206148 A1 · MEMORY DEVICES AND METHODS FOR FORMING THE SAME

Abstract

A memory device includes a first semiconductor layer, a first memory array, a second memory array, and a first peripheral circuit. The first memory array is disposed on a first side of the first semiconductor layer. The first memory array includes first memory cells, and first split structures. The second memory array is disposed on a second side of the first semiconductor layer opposite to the first side. The second memory array includes second memory cells, and second split structures. The first peripheral circuit including a first peripheral device disposed on the first memory array.

Claims20

Dependent claims

A memory device, comprising:

a first semiconductor layer;
a first memory array disposed on a first side of the first semiconductor layer, comprising:
first memory cells;
and
first split structures;
a second memory array disposed on a second side of the first semiconductor layer opposite to the first side, comprising:
second memory cells;
and
second split structures;
and
a first peripheral circuit comprising a first peripheral device disposed on the first memory array.

8 more elements

A memory device, comprising:

a first semiconductor layer;
a first memory array comprising first memory cells disposed on a first side of the first semiconductor layer, wherein each first memory cell comprises:
a first semiconductor body extending in a first direction, wherein a first end of the first semiconductor body is in contact with the first semiconductor layer;
a first word line extending in a second direction perpendicular to the first direction;
a first plate line extending in the second direction;
and
a first dielectric layer disposed between the first semiconductor body and the first word line and the first plate line;
a second memory array comprising second memory cells disposed on a second side of the first semiconductor layer opposite to the first side, wherein each second memory cell comprises:
a second semiconductor body extending in the first direction, wherein a first end of the second semiconductor body is in contact with the first semiconductor layer;
a second word line extending in the second direction;
a second plate line extending in the second direction;
and
a second dielectric layer disposed between the second semiconductor body and the second word line and the second plate line;
and
a first peripheral circuit comprising a first peripheral device disposed on the first memory array.

12 more elements

A method for forming a memory device, comprising:

forming a first memory array comprising first memory cells on a first surface of a first semiconductor layer, wherein the first memory array comprises a first channel structure extending in a first direction, and a first word line and a first plate line extending in a second direction perpendicular to the first direction;
forming a first peripheral circuit comprising a first peripheral device on the first memory array;
forming a second memory array comprising second memory cells on a second surface of the first semiconductor layer opposite to the first surface, wherein the second memory array comprises a second channel structure extending in the first direction, and a second word line and a second plate line extending in the second direction;
and
forming a second peripheral circuit comprising a second peripheral device on the second memory array.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/089,472Filed 27 Dec 2022

Priority

CN 202211622286.816 Dec 2022

Published

20 Jun 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10B 12/20
Dynamic random access memory [DRAM] devices: dRAM devices comprising floating-body transistors, e.g. floating-body cells
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40
EEPROM devices comprising charge-trapping gate insulators: characterised by the peripheral circuit region
H10B 43/50
EEPROM devices comprising charge-trapping gate insulators: characterised by the boundary region between the core and peripheral circuit regions

Memory devices and methods for forming the same

Life of this patent

Memory devices and methods for forming the same

Life of this patent

Abstract

Claims20