Method for producing pillar-shaped semiconductor device

A method for producing a pillar-shaped semiconductor device having both a circular SGT (CSGT) and an elongated SGT (ESGT) on a substrate,

• wherein the pillar-shaped semiconductor device includes:
• on the substrate, a first semiconductor pillar region having a first semiconductor pillar with a CSGT shape, and a second semiconductor pillar region having a second semiconductor pillar with an ESGT shape;
• a first gate insulating layer around the first semiconductor pillar;
• a second gate insulating layer around the second semiconductor pillar;
• a first gate conductor layer around the first gate insulating layer;
• a second gate conductor layer around the second gate insulating layer;
• a first impurity region connected to a lower portion of the first semiconductor pillar;
• a second impurity region connected to a lower portion of the second semiconductor pillar;
• a third impurity region connected to a top portion of the first semiconductor pillar;
• and a fourth impurity region connected to a top portion of the second semiconductor pillar, and
• the pillar-shaped semiconductor device has:
• a first SGT in which the first semiconductor pillar between the first impurity region and the third impurity region is a channel;
• and a second SGT in which the second semiconductor pillar between the second impurity region and the fourth impurity region is a channel,
• wherein the method comprises:
• a step of forming, on a surface of the substrate, the first impurity region and the second impurity region each containing a donor or acceptor impurity;
• a step of forming a semiconductor pillar layer, which will serve as the first and second semiconductor pillars, on the first impurity region and the second impurity region to cover an entire surface, and forming the third impurity region and the fourth impurity region on the semiconductor pillar layer;
• a step of forming a first hard mask layer on the third impurity region and the fourth impurity region to cover an entire surface;
• a step of forming a first support layer in a band shape in plan view on the first hard mask layer on the first semiconductor pillar region, and forming a second support layer in a rectangular shape in plan view on the first hard mask layer on the second semiconductor pillar region;
• a step of forming a second hard mask layer to cover an entire surface;
• a step of anisotropically etching the second hard mask layer to form first sidewalls composed of the second hard mask layer and located on side walls of the first and second support layers;
• a step of forming a first insulating layer to cover an entire surface;
• a step of polishing the first insulating layer until surfaces of top portions of the first and second support layers are exposed;
• a step of forming a third hard mask layer to cover an entire surface;
• a step of forming a third support layer on the third hard mask layer in the first semiconductor pillar region such that the third support layer has a band shape so as to perpendicularly cross the first support layer in plan view, and forming a fourth support layer on the third hard mask layer in the second semiconductor pillar region such that the fourth support layer has a rectangular opening inside so as to surround the first sidewall in plan view;
• a step of forming a fourth hard mask layer to cover an entire surface;
• a step of anisotropically etching the fourth hard mask layer to form second sidewalls composed of the fourth hard mask layer and located on side walls of the third and fourth support layer;
• a step of forming, by photolithography, a photoresist above the first semiconductor pillar region so as to cover the second sidewall in a region for forming the CSGT and forming the photoresist above the second semiconductor pillar region so as to cover the second sidewall in a region for forming the ESGT;
• a step of anisotropically etching the exposed second sidewalls away and stripping the photoresist;
• a step of removing the third and fourth support layers and sequentially anisotropically etching the third hard mask layer and the first sidewalls by using the remaining second sidewalls as a mask to remove the first insulating layer, the first support layer, and the second support layer;
• a step of sequentially anisotropically etching the first hard mask layer, the third impurity region and the fourth impurity region, the semiconductor pillar layer, and the first impurity region and the second impurity region by using the remaining first sidewalls as a mask to form the first semiconductor pillar and the second semiconductor pillar;
• a step of forming the first gate insulating layer around the first semiconductor pillar, and forming the second gate insulating layer around the second semiconductor pillar;
• and
• a step of forming the first gate conductor layer around the first gate insulating layer, and forming the second gate conductor layer around the second gate insulating layer.