Stacked SRAM Cell with a Dual-Side Interconnect Structure

A method for processing a stacked static random access memory, SRAM, cell, the method comprising:

• processing one or two pass gate, PG, transistor structures on a substrate;
• processing two first transistor structures on the substrate or above the PG transistor structures;
• processing two second transistor structures on the substrate or above the PG transistor structures;
• forming a pair of cross-coupled inverters from the first transistor structures and the second transistor structures;
• processing one or more first power rails and/or one or more second power rails above the second transistor structures;
• processing respective first vias to connect the one or more first power rails to at least one of the first transistor structures from above, and/or respective second vias to connect the one or more second power rails to at least one of the second transistor structures from above;
• removing the substrate;
• processing one or two bit lines below the one or two PG transistor structures;
• and
• processing respective one or two third vias to connect each bit line respectively to one PG transistor structure from below.