Back to results
US 2024/0205185 A1Published application
Address Assignment Method, Node Determining Method and Apparatus, and Storage Medium
AssigneeHuawei Technologies Co., Ltd.
InventorDelei Yu
Life of this patent
Estimating the term…
Abstract
A method includes: a first node obtains an address of a second node based on an address of the first node, where the address of the first node includes m bits, where the address of the second node includes m+n bits, where high-order m bits of the address of the second node are the same as low-order m bits of the address of the first node, and where m and n each are an integer greater than 0; and the first node sends the address of the second node to the second node.
Claims33
A method, comprising:
- obtaining, by a first node and based on a first address of the first node, a second address of a second node, comprises m bits, wherein the second address comprises m+n bits, wherein m first high-order of the second address node are the same as m low-order bits of the first address, and wherein m and n are integers greater than 0;
- and
- sending, by the first node and to the second node, the second address.
-6. (canceled)
A method, comprising:
- receiving, by a first node, a first message, wherein the first message comprises a destination address, wherein the destination address comprises x bits, and wherein x is an integer greater than 0;
- and
- determining, by the first node and based on a first address of the first node and the destination address, a next-hop node of the first message,
- wherein the first address of the first node comprises y bits, and
- wherein y is an integer greater than 0.
2 more elements
An apparatus, comprising:
- a memory configured to store instructions;
- and
- one or more processors coupled to the memory and configured to execute the instructions to:
- obtain, based on a first address of the apparatus, a second address of a second node, wherein the first address comprises m bits, wherein the second address comprises m+n bits, wherein m high-order bits of the second address are the same as m low-order bits of the first address, and wherein m and n are integers greater than 0;
- and
- send, to the second node, the second address.
3 more elements
-29. (canceled)
An apparatus, comprising
- a memory configured to store instructions;
- and
- one or more processors coupled to the memory and configured to execute the instructions to:
- receive a first message, wherein the first message comprises a destination address, wherein the destination address comprises x bits, and wherein x is an integer greater than 0;
- and
- determine, based on a first address of the apparatus and the destination address, a next-hop node of the first message,
- wherein the first address comprises y bits, and
- wherein y is an integer greater than 0.
5 more elements
Dependencies are inferred from the claim text.