Method and electronic apparatus with parallel single-stage switching

An electronic apparatus comprising:

• a plurality of processor device-memory device groups, and each of the plurality of processor device-memory device groups comprising a plurality of memory devices respectively comprising one or more memories, a plurality of processor devices respectively comprising one or more processors, and a plurality of switches,
• wherein each of the plurality of processor devices comprises a plurality of ports, and
• each of first processor devices included in a first processor device-memory device group of the plurality of processor device-memory device groups is connected to a first subset of one of first switches of the plurality of switches included in the first processor device-memory device group and to a first subset of ports of one switch of second switches of the plurality of switches included in a second processor device-memory device group of the plurality of processor device-memory device groups.

An electronic apparatus comprising:

• a plurality of memory device groups, and each of the plurality of memory device groups comprising a plurality of memory devices respectively comprising one or memories and a plurality of switches,
• wherein each of the plurality of memory devices comprises a plurality of ports, and
• each of first memory devices included in a first memory device group of the plurality of memory device groups is connected to a first subset of ports of one switch of first switches included in the first memory device group, and to a first subset of ports of one switch of second switches of the plurality of switches included in a second processor device-memory device group of the plurality of processor device-memory device groups.

An electronic apparatus comprising:

• a plurality of processor device-memory device groups, and each of the plurality of processor device-memory device groups comprising a plurality of memory devices respectively comprising one or more memories, a plurality of processor devices respectively comprising one or more processors, and a plurality of switches,
• wherein each of the plurality of switches comprises a plurality of ports, and
• the plurality of memory devices in one processor device-memory device group of the plurality of processor device-memory device groups is connected to first subsets of ports of each of the plurality of switches in the one processor device-memory device group and another one processor device-memory device group of the plurality of processor device-memory device groups.