System with a low-drift on-chip oscillator with lowered sensitivity to random telegraph noise

A method for lowering sensitivity to Random Telegraph Noise of a system with a low-drift on-chip oscillator in an oscillator stage for generating a current (Id) for the LD-RC oscillator, said system comprising a control resistor (R) connected through an intermediary arrangement to one of a first MOS transistor (M1) or of a second MOS transistor (M2) between two terminals of a supply voltage source (Vdd), the gate of the first MOS transistor (M1) being connected to the gate of the second MOS transistor (M2), whereas the source of the first MOS transistor (M1) and the source of the second MOS transistor (M2) are connected in direction to a first terminal of the supply voltage source (Vdd), the control resistor (R) being connected to a second terminal opposite to the first terminal of the supply voltage source (Vdd), and the system comprising in the oscillator stage still a feedback unit, which is an operational amplifier in operation for the comparison between a voltage (Vr) generated by the current (Is) through the control resistor R and the supply voltage (Vc) generated by the current (Id) through the LD-RC oscillator, the output (VrP) of the operational amplifier being connected to gates of the first and second MOS transistors (M1, M2),

• for implementing the method, the intermediary arrangement includes first, second, third, fourth controlled chopping switches (S1A, S1B, S2B, S2A) controlled by a switch control unit, placed between the control resistor (R) and the first and second MOS transistors (M1, M2), and between the LD-RC oscillator and the first and second MOS transistors (M1, M2), wherein a first controlled chopping switch (S1A) is placed between the control resistor (R) and the drain of the first MOS transistor (M1) of a first branch, whereas a second controlled chopping switch (S1B) is placed between the LD-RC oscillator and the drain of the second MOS transistor (M2) of a second branch, and wherein a third controlled chopping switch (S2B) is placed between the control resistor (R) and the drain of the second MOS transistor (M2), whereas a fourth controlled chopping switch (S2A) is placed between the LD-RC oscillator and the drain of the first MOS transistor (M1), and
• the first and second switches (S1A, S1B) being controlled by a first control signal (PH1) to be in conducting mode during a first phase P1, whereas the third and fourth switches (S2B, S2A) are controlled by a second control signal (PH2) to be in non-conductive mode during the first phase P1,
• the third and fourth switches (S2B, S2A) being controlled by the second control signal (PH2) to be in conducting mode during a second phase P2, whereas the first and second switches (S1A, S1B) are controlled by the first control signal (PH1) intended to be in non-conductive mode during the second phase P2,
• all the controlled chopping switches (S1A, S1B, S2B, S2A) being controlled by the switch control unit at least during a predefined time, which is a sleep time (Tsleep), or all the time of some parts of the system other than the oscillator stage, and
• during the predefined time or all the time, phases P1 and phases P2 alternating successively in order to perform a chopping operation by commuting the first and second MOS transistors (M1, M2) from phase P1 to phase P2, and from phase P2 to phase P1,
• wherein the ring oscillator made of an odd number n of CMOS inverters has the balance ensured via a feedback unit, which is implemented by an operational amplifier in the depicted case.