Methods and systems of current sensing in switching power converters

A power module comprising:

• a switch-node terminal, a PWM-input terminal, and a monitor-output terminal;
• a high-side FET defining a drain, a source coupled to the switch-node terminal, and a gate;
• a low-side FET defining drain coupled to the switch-node terminal, a source, and a gate;
• a controller coupled to the gate of the high-side FET, the gate of the low-side FET, the PWM-input terminal, and the monitor-output terminal, the controller configured to:
• responsive to de-assertion of the PWM-input terminal, make the high-side FET non-conductive and the low-side FET conductive to define a discharge mode in a first cycle;
• drive, during the discharge mode, a signal indicative of instantaneous current to the monitor-output terminal, the signal indicative of instantaneous current directly proportional to voltage drop across the low-side FET during at least a portion of the discharge mode;
• responsive to assertion of the PWM-input terminal, make the low-side FET non-conductive and the high-side FET conductive to define a charge mode in a second cycle subsequent to the first cycle;
• and
• drive, during the charge mode of the second cycle, an emulated signal to the monitor-output terminal, the emulated signal generated based on the current through the low-side FET in the first cycle.

A system comprising:

• an inductor defining a first lead and a second lead coupled to a load;
• a voltage regulator defining a voltage-monitor input coupled to the second lead, a PWM output, and a current-monitor input;
• a power module defining a switch node coupled to the first lead, a PWM input coupled to the PWM output, and a monitor output coupled to the current-monitor input, the power module comprising:
• a high-side FET defining a source coupled to the switch node and a gate;
• a low-side FET defining drain coupled to the switch node, and a gate;
• a controller coupled to the gate of the high-side FET, the gate of the low-side FET, the PWM input, and the current-monitor input of the voltage regulator, the controller configured to:
• responsive to de-assertion of the PWM input, make the high-side FET non-conductive and the low-side FET conductive to discharge the inductor during a discharge mode of a first cycle;
• drive, during the discharge mode, a signal indicative of instantaneous current to the current-monitor input, the signal indicative of instantaneous current proportional to an instantaneous current through the inductor during at least a portion of the discharge mode;
• responsive to assertion of the PWM input, make the low-side FET non-conductive and the high-side FET conductive to charge the inductor during a charge mode of a second cycle subsequent to the first cycle;
• and
• drive, during the charge mode of the second cycle, an emulated signal to the current-monitor input, the emulated signal generated based on the current through the inductor in the first cycle.