Self-aligned jfet device
AssigneeSemiconductor Components Industries, LLC
InventorsAlexander Viktorovich BOLOTNIKOV, Jimmy Robert Hannes FRANCHI, Krister GUMAELIUS
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Abstract
A JFET transistor device having a reduced pitch may be manufactured using self-alignment techniques, while avoiding misalignments that may lead to decreased breakdown voltage and/or increased RDSon. Consequently, described devices provide, for a given active area and gate voltage, additional current channels, increased current, and reduced RDSon, as compared to conventional devices, while retaining high BVgs values.
Claims20
A Junction Field Effect Transistor (JFET) semiconductor device, comprising:
- a substrate including a drain region of the JFET;
- a drift region disposed on the substrate;
- a lower gate disposed on the drift region;
- a source region having a lower source region that is disposed on the lower gate and extends laterally beyond the lower gate, and an upper source region disposed on the lower source region;
- and
- an upper gate formed on the lower source region and at least partially surrounding the upper source region, and extending laterally beyond the lower gate to define a gate offset between the upper gate and the lower gate.
A Junction Field Effect Transistor (JFET) semiconductor device, comprising:
- a substrate including a drain region of the JFET semiconductor device;
- a drift region disposed on the substrate;
- and
- a plurality of unit cells disposed on the drift region in a grid, with each unit cell including
- a lower gate disposed on the drift region;
- a source region having a lower source region that is disposed on the lower gate and extends laterally beyond the lower gate, and an upper source region disposed on the lower source region;
- and
- an upper gate formed on the lower source region and at least partially surrounding the upper source region, and extending laterally beyond the lower gate to define a gate offset between the upper gate and the lower gate.
A method of making a semiconductor device, the method comprising:
- forming a lower source region implant and an upper gate implant through a first opening in a mask disposed on a substrate;
- forming a first spacer on sidewalls of the mask to define a second opening that is smaller than the first opening;
- forming a lower gate through the second opening;
- forming a second spacer on the first spacer to define a third opening that is smaller than the second opening;
- and
- forming an upper source region through the third opening and within the upper gate implant to thereby define a remainder of the upper gate implant as an upper gate of a Junction Field Effect Transistor (JFET) with the substrate providing a drain of the JFET.
Dependencies are inferred from the claim text.