Transistor gate-channel arrangements with multiple dipole materials

An integrated circuit (IC) structure, comprising:

• a substrate;
• and
• a stack of nanoribbons of one or more semiconductor materials over the substrate,
• wherein a portion of at least one of the nanoribbons of the stack is a channel region of a transistor, the transistor comprising a transistor gate stack that includes:
• a gate electrode material,
• an interface layer in contact with the channel region,
• a high-k dielectric between the interface layer and the gate electrode material,
• atoms of a first dipole material, and
• atoms of a second dipole material, different from the first dipole material.

A method of manufacturing a transistor, the method comprising:

• providing an interface layer;
• providing a high-k dielectric forming an interface with the interface layer;
• providing a first dipole material over the high-k dielectric;
• providing a second dipole material over the first dipole material, wherein one of the first dipole material and the second dipole material is a P-shifter dipole material and another one of the first dipole material and the second dipole material is an N-shifter dipole material;
• providing a cap sealing the first dipole material and the second dipole material;
• performing an anneal to diffuse atoms of the first dipole material and atoms of the second dipole material into the high-k dielectric;
• and
• following the anneal, providing a gate electrode material so that the high-k dielectric is between the interface layer and the gate electrode material.