Self-aligned gate metal with top-dielectric isolation

A semiconductor device, comprising:

• a substrate;
• a first fin field effect transistor (FET) on top of the substrate;
• a first stack of nanosheets in the first fin FET;
• a first top semiconductor channel in the first stack of nanosheets;
• a first bottom semiconductor channel in the first stack of nanosheets;
• a second fin FET on top of the substrate;
• a second stack of nanosheets in the second fin FET;
• a second top semiconductor channel in the second stack of nanosheets;
• a second bottom semiconductor channel in the second stack of nanosheets;
• a gate body coupled to the first top semiconductor channel, the second top semiconductor channel, the first bottom semiconductor channel, and the second bottom semiconductor channel, and including a layer of metal positioned on top of the first top semiconductor channel and on top of the second top semiconductor channel;
• and
• a spacer body including a top dielectric layer positioned on top of the layer of metal, wherein a thickness of the layer of metal above the first top semiconductor channel is based on a distance from a bottom surface of the top dielectric layer to a top surface of either the first top semiconductor channel or the second top semiconductor channel.

A method of manufacturing a semiconductor device, comprising:

• forming a stack of nanosheets on a substrate, including:
• providing at least a first semiconductor channel and a second semiconductor channel, and at least a first sacrificial suspension layer on top of the first semiconductor channel;
• providing a second sacrificial suspension layer between the first semiconductor channel and the second semiconductor channel;
• and
• providing a third sacrificial suspension layer under the second semiconductor channel;
• forming a dielectric dummy layer on top of the first sacrificial suspension layer;
• removing the dielectric dummy layer to define an empty area on top of the first sacrificial suspension layer;
• depositing a spacer dielectric into at least the empty area on top of the first sacrificial suspension layer;
• forming a fin field effect transistor (FET) from the stack of nanosheets, wherein at least some of the spacer dielectric is positioned on top of the fin FET;
• forming a source and a drain coupled to the fin FET;
• removing the first, second, and third sacrificial suspension layers;
• and
• depositing a gate metal in areas including, above the first semiconductor channel, in between the first semiconductor channel and the second semiconductor channel, and under the second semiconductor channel, wherein a thickness of the gate metal positioned on top of the first semiconductor channel is pre-defined.