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US 2024/0204077 A1Published application
Fast switching transistors
AssigneeGeorge Mason University
InventorsParameswari Raju, Qiliang Li
Life of this patent
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Abstract
A transistor includes a gate, a channel, a gate dielectric at least partially disposed between the gate and the channel, and at least one two-dimensional (2D) layer of a heterostructure disposed within the gate dielectric and spaced from both the gate and the channel. The channel and at least one 2D layer are configured to define a negative quantum capacitance such that a subthreshold slope of the transistor is less than 60 mV/dec.
Claims20
A transistor, comprising:
- a gate;
- a channel;
- a gate dielectric at least partially disposed between the gate and the channel;
- and
- at least one two-dimensional (2D) layer of a heterostructure disposed within the gate dielectric and spaced from both the gate and the channel,
- wherein the channel and the at least one 2D layer are configured to define a negative quantum capacitance such that a subthreshold slope of the transistor is less than 60 mV/dec.
3 more elements
A transistor, comprising:
- a stack including a gate, a gate dielectric, and a channel, wherein the channel is formed from a plurality of two-dimensional (2D) layers of material;
- and
- an insert including at least one 2D layer of material, the insert disposed within the gate dielectric between the gate and the channel,
- wherein the stack is configured to define a negative quantum capacitance, such that a subthreshold slope of the transistor is less than 60 mV/dec.
1 more element
A transistor, comprising:
- a stack including a gate, a gate dielectric, and a channel, wherein the channel is formed from three two-dimensional (2D) layers of MoS2;
- and
- an insert formed from one single 2D layer of T′WTe2, the insert disposed within the gate dielectric between the gate and the channel.
Dependencies are inferred from the claim text.