Semiconductor Device Structure

A circuit cell for an integrated circuit, the circuit cell comprising a semiconductor device structure including a first field-effect transistor, FET comprising:

• a first source/drain, S/D, structure, a second S/D structure, a first channel structure comprising a set of vertically spaced apart channel layers extending between the first and second S/D structures in a channel direction, and a first gate structure,
• the first S/D structure comprising a first S/D body and a first set of vertically spaced apart S/D prongs protruding laterally from the first S/D body, transverse to the channel direction, to contact the first channel structure,
• the second S/D structure comprising a second S/D body and a second set of vertically spaced apart S/D prongs protruding laterally from the second S/D body in a same direction as the first set of S/D prongs, to contact the first channel structure, and
• the first gate structure comprising a first gate body and a first set of gate prongs protruding laterally from the first gate body in an opposite direction to the first and second sets of S/D prongs, into spaces between the channel layers of the first channel structure;
• and
• a second FET comprising:
• a third S/D structure, a fourth S/D structure, a second channel structure comprising a set of vertically spaced apart channel layers extending between the third and fourth S/D structures in the channel direction, and a second gate structure,
• the third S/D structure comprising a third S/D body and a third set of vertically spaced apart S/D prongs protruding laterally from the third S/D body in the same direction as the first set of gate prongs, to contact the second channel structure,
• the fourth S/D structure comprising a fourth S/D body and a fourth set of vertically spaced apart S/D prongs protruding laterally from the fourth S/D body in the same direction as the third set of S/D prongs, to contact the second channel structure, and
• the second gate structure comprising a second gate body and a second set of gate prongs protruding from the second gate body in the same direction as the first and second sets of S/D prongs, into spaces between the channel layers of the second channel structure;
• and
• wherein the first S/D body is arranged between the third and fourth S/D bodies and the fourth S/D body is arranged between the first and second S/D bodies.