Vertical gate field effect transistor

A method comprising:

• forming a first masking structure over a substrate, wherein an opening in the first masking structure completely separates an inner region from an outer region of the first masking structure;
• removing portions of the substrate that directly underlie the opening of the first masking structure to form a first trench structure in the substrate;
• forming a gate dielectric layer over the substrate;
• forming a gate electrode structure within the first trench structure and over the first trench structure;
• forming first and second source/drain regions in the substrate;
• and
• forming a heavily doped region continuously surrounding the gate electrode structure and extending from a backside of the substrate to a frontside of the substrate.

A method comprising:

• forming a trench isolation structure in a first continuously connected ring on a frontside of a substrate, wherein the trench isolation structure separates an inner region of the substrate from an outer region of the substrate;
• forming a first masking structure over the substrate, wherein the first masking structure comprises an opening contacting an outer perimeter of the inner region of the substrate;
• removing portions of the substrate that directly underlie the opening of the first masking structure;
• removing the first masking structure;
• forming a gate dielectric layer over the substrate;
• forming a gate electrode material over the gate dielectric layer;
• removing outer portions of the gate electrode material to form a gate electrode structure comprising a horizontal portion and a plurality of vertical portions;
• and
• forming first and second source/drain regions in the substrate.