Low resistance metalization for connecting a vertical transport fet single-cpp inverter
AssigneeInternational Business Machines Corporation
InventorsBrent A. Anderson, Nicholas Anthony Lanzillo, Albert M. Chu, Ruilong Xie, Lawrence A. Clevenger
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Abstract
Embodiments of the invention provide a multi-layer integrated circuit (IC) structure that includes a first transistor, a second transistor, and a contact element. The first transistor includes a first source or drain (S/D). The second transistor includes a second S/D and a gate. The contact element includes substantially horizontal features operable to connect the first S/D of the first transistor to the gate of the second transistor.
Claims20
A multi-layer integrated circuit (IC) structure comprising:
- a first transistor having a first source or drain (S/D);
- a second transistor having a second S/D and a gate;
- and
- a contact element having substantially horizontal features operable to connect the first S/D of the first transistor to the gate of the second transistor.
A method of forming a multi-layer integrated circuit (IC) structure, the method comprising:
- forming a first transistor having a first source or drain (S/D);
- forming a second transistor having a second S/D and a gate;
- and
- forming a contact element having substantially horizontal features operable to connect the first S/D of the first transistor to the gate of the second transistor.
Dependencies are inferred from the claim text.