Gate tie-down for top field effect transistor

A semiconductor device, comprising:

• a backside power rail;
• and
• a stacked field effect transistor (FET) structure comprising:
• a bottom FET device;
• a top FET device overlying the bottom FET device;
• dielectric material interposed between the bottom FET device and the top FET device;
• and
• a gate tie-down assembly of the top FET device extending through the bottom FET device to connect to the backside power rail.

A semiconductor device fabrication method, comprising:

• forming a stack comprising a bottom field effect transistor (FET) device, a top FET device overlying the bottom FET device and dielectric material interposed between the bottom FET device and the top FET device;
• creating an opening through the stack;
• filling the opening with an outer core dielectric and an inner core dielectric;
• removing the inner core dielectric and a portion of the outer core dielectric to expose gate metal and portions of channels of the top FET device;
• forming inner spacers to isolate remainders of the channels;
• and
• forming a backside power rail contact by metallizing space previously occupied by the inner core dielectric and the portion of the outer core dielectric.