STACKED VERTICAL-TRANSPORT FIELD EFFECT TRANSISTORS (VTFETs)

A method for fabricating a semiconductor device, the method comprising:

• forming a first dummy interconnect for a bottom S/D epi of a first bottom VTFET, wherein the first dummy interconnect comprises an interconnect placeholder material;
• generating a first contact opening that exposes a bottom S/D epi of the first bottom VTFET and the first dummy interconnect;
• removing the first dummy interconnect;
• and
• performing backside contact metallization to generate a first backside contact that wires the bottom S/D epi of the first bottom VTFET to a first local interconnect that is wired to a first frontside contact that is wired to a back end of line (BEOL) interconnect, wherein the first backside contact is generated in a region formerly occupied by the removed first dummy interconnect and the first contact opening.

A computer program product comprising program instructions stored on a computer readable storage medium, the program instructions executable by a processor to cause the processor to perform a method on a wafer, the method comprising:

• forming a first dummy interconnect for a bottom S/D epi of a first bottom VTFET, wherein the first dummy interconnect comprises an interconnect placeholder material;
• generating a first contact opening that exposes a bottom S/D epi of the first bottom VTFET and the first dummy interconnect;
• removing the first dummy interconnect;
• and
• performing backside contact metallization to generate a first backside contact that wires the bottom S/D epi of the first bottom VTFET to a first local interconnect that is wired to a first frontside contact that is wired to a back end of line (BEOL) interconnect, wherein the first backside contact is generated in a region formerly occupied by the removed first dummy interconnect and the first contact opening.