Input/output interface cell, semiconductor device and manufacturing method of the semiconductor device

A manufacturing method of the semiconductor device, the method comprising:

• generating a layout by defining a plurality of input/output (I/O) interface cell regions in a semiconductor substrate and disposing a plurality of electrostatic discharge (ESD) diodes, one or more drivers, and a through silicon via (TSV) in each of the plurality of I/O interface cell regions;
• manufacturing a plurality of masks based on the layout;
• forming semiconductor components constituting the plurality of ESD diodes and the one or more drivers in the I/O interface cell regions using the plurality of masks;
• determining ESD performance for each of the plurality of I/O interface cell regions;
• designing patterns of each of the plurality of I/O interface cell regions according to the determined ESD performance;
• manufacturing at least one new mask based on the designed patterns;
• and
• completing the semiconductor device by forming wiring patterns and via patterns of the semiconductor device using the plurality of masks and the new mask.

An input/output (I/O) interface cell comprising:

• a first driver including a first inverter and a plurality of second inverters connected in parallel to an output terminal of the first inverter;
• a second driver including a plurality of third inverters;
• a first electrostatic discharge (ESD) diode including a plurality of first unit diodes, each including a first diode connected between a first power source and an output terminal of the first driver and a second diode connected between a second power source and the output terminal of the first driver;
• a second ESD diode including a plurality of second unit diodes;
• and
• a through silicon via (TSV) electrically connected to the output terminal of the first driver,
• wherein the plurality of third inverters of the second driver are selectively connected in parallel to the plurality of second inverters depending on a wiring pattern, and
• the plurality of second unit diodes are selectively connected in parallel with the plurality of first unit diodes depending on the wiring pattern.