Low-resistance via to backside power rail

A semiconductor device, comprising:

• a front-end-of-line (FEOL) layer including a FEOL device;
• a back-end-of-line (BEOL) layer on a front side of the FOEL layer;
• a backside power line on a back side of the FEOL layer;
• a conductive structure that contacts the FEOL device at the front side of the FEOL layer and that extends through the FEOL layer to contact the backside power line, including a frontside part that includes a metal liner and a first fill material and a backside part that includes a second fill material having an outer surface that aligns with an outer surface of the metal liner;
• a dielectric liner on sidewalls of the backside part of the conductive structure, including a first dielectric material;
• and
• an interlayer dielectric around the dielectric liner, including a second dielectric material different from the first dielectric material.

A method for forming a semiconductor device, comprising:

• forming a front-end-of-line (FEOL) layer that includes a FEOL device;
• forming a frontside conductive contact on the FEOL device, including a metal liner between the frontside conductive contact and the FEOL device;
• and
• forming a backside conductive contact in electrical contact with the frontside conductive contact, an outer surface of the backside conductive contact aligning with an outer surface of the metal liner.