Semiconductor memory device

A semiconductor memory device comprising:

• a stacked body including a first stacked portion including a plurality of first conductive layers stacked to be apart from each other in a first direction and having a first end portion stepwise processed along a second direction crossing the first direction, and a second stacked portion provided on an upper layer side of the first stacked portion, including a plurality of second conductive layers stacked to be apart from each other in the first direction, and having a second end portion arranged beside the first end portion in the second direction and stepwise processed along the second direction;
• a plurality of pillar structures each including a semiconductor layer extending along the first direction in the stacked body;
• a first interlayer insulating layer covering the first end portion;
• a second interlayer insulating layer provided on an upper layer side of the first interlayer insulating layer and covering the second end portion;
• a first stopper insulating layer provided at least between the first interlayer insulating layer and the second interlayer insulating layer and above the first end portion, including a first portion extending flat along a plane perpendicular to the first direction above the first end portion throughout the first end portion in the second direction, and formed of a material with a main component which is different from that of a material of the first interlayer insulating layer and that of a material of the second interlayer insulating layer;
• a plurality of first contacts penetrating the second interlayer insulating layer, the first portion of the first stopper insulating layer and the first interlayer insulating layer, and connected to different first conductive layers, respectively, of the plurality of first conductive layers;
• and
• a plurality of second contacts penetrating the second interlayer insulating layer, and connected to different second conductive layers, respectively, of the plurality of second conductive layers.

A semiconductor memory device comprising:

• a stacked body including a first stacked portion including a plurality of first conductive layers stacked to be apart from each other in a first direction and having a first end portion stepwise processed along a second direction crossing the first direction, and a second stacked portion provided on an upper layer side of the first stacked portion, including a plurality of second conductive layers stacked to be apart from each other in the first direction, and having a second end portion arranged beside the first end portion in the second direction and stepwise processed along the second direction;
• a plurality of pillar structures each including a semiconductor layer extending along the first direction in the stacked body;
• a first interlayer insulating layer covering the first end portion;
• a second interlayer insulating layer provided on an upper layer side of the first interlayer insulating layer and covering the second end portion;
• a stopper insulating layer including at least a first portion provided on an upper layer side of the second interlayer insulating layer and above the second end portion and a second portion provided to be opposed to an uppermost surface of the second stacked portion in the first direction, without including a portion provided above the first end portion, and formed of a material with a main component which is different from that of a material of the first interlayer insulating layer and that of a material of the second interlayer insulating layer;
• a plurality of first contacts penetrating the second interlayer insulating layer and the first interlayer insulating layer, and connected to different first conductive layers, respectively, of the plurality of first conductive layers;
• a plurality of second contacts penetrating the first portion of the stopper insulating layer and the second interlayer insulating layer, and connected to different second conductive layers, respectively, of the plurality of second conductive layers;
• and
• a plurality of third contacts penetrating the second portion of the stopper insulating layer, and each connected to the semiconductor layer of a respective pillar structure of the plurality of pillar structures.