Semiconductor device and data storage systems including a semiconductor device

A semiconductor device comprising:

• a first semiconductor structure including a substrate, circuit elements on the substrate, and circuit interconnection lines connected to the circuit elements;
• and
• a second semiconductor structure on the first semiconductor structure and having first and second regions,
• wherein the second semiconductor structure includes:
• a plate layer;
• gate electrodes stacked on the plate layer and spaced apart from each other in a first direction, perpendicular to an upper surface of the plate layer, and having pad regions extending to different lengths in a second direction, perpendicular to the first direction, in the second region such that upper surfaces of the pad regions are exposed;
• gate separation regions, in the first and second regions, passing through the gate electrodes and extending in the second direction;
• an upper isolation region on portions of the gate electrodes, dividing an uppermost gate electrode, among the gate electrodes, into first and second sub-gate electrodes between the gate separation regions, and extending in the second direction, and
• contact plugs, in the second region, extending in the first direction through the gate electrodes and connected to portions of the circuit interconnection lines,
• the upper isolation region has a region extending in a third direction, intersecting the second direction,
• the first sub-gate electrode has first and second pad regions having different sizes, and the second sub-gate electrode has third and fourth pad regions having different sizes, and
• the first sub-gate electrode is connected to one of the contact plugs in the first pad region, and the second sub-gate electrode is connected to one of the contact plugs in the fourth pad region.

A data storage system comprising:

• a semiconductor storage device including a first semiconductor structure including circuit elements, a second semiconductor structure including channel structures and having first and second regions, and an input/output pad electrically connected to the circuit elements;
• and
• a controller electrically connected to the semiconductor storage device via the input/output pad and configured to control the semiconductor storage device,
• wherein the second semiconductor structure further includes:
• gate electrodes stacked and spaced apart from each other in a first direction, the gate electrodes including a lower gate electrode, memory gate electrodes, and an upper gate electrode sequentially stacked, and having pad regions extending to different lengths in a second direction, perpendicular to the first direction, in the second region such that upper surfaces of the pad regions are exposed;
• gate separation regions, in the first and second regions, passing through the gate electrodes and extending in the second direction;
• first and second upper isolation regions on the memory gate electrodes, dividing the upper gate electrode into first, second and third sub-gate electrodes between adjacent gate separation regions, and extending in the second direction;
• and
• contact plugs, in the second region, extending in the first direction through the pad regions of the gate electrodes and connected to portions of the circuit interconnection lines, and
• the first and second upper isolation regions have regions extending in a third direction, intersecting the second direction, and being symmetrical to each other in a fourth direction, perpendicular to the second direction.