Semiconductor packages and methods for fabricating the same

A semiconductor package comprising:

• a first redistribution layer substrate including a redistribution line and a redistribution via on the redistribution line;
• a bonding pad on the redistribution line and the redistribution via;
• a coupling member on the bonding pad;
• a semiconductor chip on the first redistribution layer substrate, wherein the semiconductor chip is spaced apart from the coupling member;
• a connection member that electrically connects the first redistribution layer substrate and the semiconductor chip;
• an encapsulant on the bonding pad, the coupling member, the connection member, and the semiconductor chip;
• and
• a second redistribution layer substrate on the encapsulant,
• wherein the coupling member includes a vertical wire and a metal portion extending around the vertical wire, and
• wherein a first end of the coupling member is electrically connected to the bonding pad, and a second end of the coupling member is electrically connected to the second redistribution layer substrate.

A method for fabricating a semiconductor package, the method comprising:

• forming a bonding pad on a first redistribution layer substrate;
• bonding a first end of a vertical wire on the bonding pad;
• electroplating on the vertical wire to form a metal portion around the vertical wire;
• mounting a semiconductor chip on the first redistribution layer substrate;
• molding the metal portion and the semiconductor chip with an encapsulant;
• and
• forming a second redistribution layer substrate on the encapsulant, wherein a second end of the vertical wire is bonded to the second redistribution layer substrate.