Semiconductor chip and method of manufacturing the same

A semiconductor chip, comprising:

• a semiconductor substrate having a first surface and a second surface facing each other,
• a front end level layer formed on the first surface of the semiconductor substrate and comprising an integrated circuit layer,
• a back end level layer electrically connected to the integrated circuit layer on the front end level layer and comprising a plurality of metal wiring layers;
• a first through via structure bundle extending in a vertical direction from a first metal wiring layer of the plurality of metal wiring layers toward the semiconductor substrate and penetrating through the front end level layer, the first surface of the semiconductor substrate, and the second surface of the semiconductor substrate;
• and
• a second through via structure bundle spaced apart from the first through via structure bundle, extending in the vertical direction from a second metal wiring layer of the plurality of metal wiring layers toward the semiconductor substrate, and penetrating through at least a part of the back end level layer, the front end level layer, the first surface of the semiconductor substrate, and the second surface of the semiconductor substrate.

A semiconductor chip, comprising:

• a semiconductor substrate;
• a front end level layer comprising an integrated circuit layer formed on the semiconductor substrate, an interlayer insulation layer insulating the integrated circuit layer, and a contact plug layer electrically connected to the integrated circuit layer within the interlayer insulation layer;
• a back end level layer formed on the front end level layer and comprising a plurality of metal wiring layers sequentially and electrically connected to the contact plug layer, wiring insulation layers insulating between the plurality of metal wiring layers, and a plurality of wiring vias interconnecting the plurality of metal wiring layers within the wiring insulation layers;
• a first through via structure bundle extending in a vertical direction from a first metal wiring layer of the plurality of metal wiring layers toward the semiconductor substrate and penetrating through the interlayer insulation layer and the semiconductor substrate;
• and
• a second through via structure bundle spaced apart from the first through via structure bundle, extending in the vertical direction from a second metal wiring layer of the plurality of metal wiring layers toward the semiconductor substrate, and penetrating through the wiring insulation layers, the interlayer insulation layer, and the semiconductor substrate, wherein the first through via structure bundle is formed in a first keep out zone located on a first side of the integrated circuit layer, and the second through via structure bundle is formed in a second keep out zone located on a second side of the integrated circuit layer.