Integrated circuit (ic) fabricated in a high mix environment
OwnerVinod Anumareddy, Joshua Wingerinventors
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Abstract
An IC manufacturing system including a transition analysis engine configured to monitor inline and EOL response metrics and determine impact levels of one or more transitions that may be encountered at respective process stages of a fabrication facility. Inline response metrics data and transition data may be monitored for one or more process stages in addition to EOL response metrics relating to pluralities of semiconductor wafers, wherein the variance of the monitored data may be correlated to one or more transitions.
Claims22
A method of fabricating an integrated circuit (IC), the method comprising:
- processing a plurality of semiconductor wafers in a fabrication flow having a sequence of process steps including a targeted process step, wherein the targeted process step comprises an operation performed at a process tool using a first process recipe with respect to a material layer over the semiconductor wafers;
- obtaining a measurement of a response metric variable for the semiconductor wafers, the response metric variable relating to a parameter associated with the semiconductor wafers;
- obtaining a first average of the response metric variable from a first subset of the plurality of semiconductor wafers;
- obtaining a second average of the response metric variable from a second subset of the plurality of semiconductor wafers;
- on the condition that a difference between the first and second averages is statistically significant, adjusting one or more process parameters of the targeted process step;
- and
- processing a subsequent semiconductor wafer at the targeted process step containing the IC at an intermediate stage of formation, wherein the subsequent semiconductor wafer is of a same technology node as the plurality of semiconductor wafers.
A method of fabricating an integrated circuit (IC), the method comprising:
- determining yield data, on a wafer-by-wafer basis, for a plurality of wafer lots processed through a fabrication flow having a sequence of process steps including a targeted process step, wherein the targeted process step comprises an operation performed at a process tool using a first process recipe with respect to a material layer over a plurality of semiconductor wafers in a wafer lot;
- obtaining a first average of a yield variable from a first subset of each respective wafer lot;
- obtaining a second average of the yield variable from a second subset of each respective wafer lot;
- on the condition that a difference between the first and second averages is statistically significant, adjusting one or more process parameters of the targeted process step;
- and
- processing a subsequent wafer lot including a semiconductor wafer at the targeted process step containing the IC at an intermediate stage of formation, wherein the subsequent wafer lot containing the semiconductor wafer is of a same technology node as the plurality of wafer lots immediately preceding the subsequent wafer lot.
An integrated circuit (IC), comprising:
- a material layer formed over a semiconductor wafer at a targeted process step of a fabrication flow, the semiconductor wafer forming a substrate for the IC;
- and
- the material layer reworked responsive to determining that a difference between a first average of a response metric variable and a second average of the response metric variable are statistically significant and attributable to a transitional condition with respect to the targeted process step performed by a process tool using a first process recipe.
Dependencies are inferred from the claim text.