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US 2024/0203520 A1Published application
Semiconductor device having memory cell array divided into plural memory mats
AssigneeMicron Technology, Inc.
InventorsSUSUMU TAKAHASHI, HIROKI FUJISAWA
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Abstract
An apparatus that includes a plurality of first memory mats each including a plurality of normal column sections each storing user data, and a second memory mat including a plurality of first redundant column sections each substituting a defective one of column sections included in the plurality of first memory mats and a plurality of first BCC column sections each storing an error correction code.
Claims20
An apparatus comprising:
- a plurality of first memory mats each including a plurality of normal column sections each storing user data;
- and
- a second memory mat including a plurality of first redundant column sections each substituting a defective one of column sections included in the plurality of first memory mats and a plurality of first ECC column sections each storing an error correction code.
An apparatus comprising:
- a first memory mat including a plurality of first normal column sections and a plurality of second normal column sections;
- a second memory mat including a plurality of first redundant column sections and a plurality of third normal column sections;
- and
- a third memory mat including a plurality of second redundant column sections and a plurality of fourth normal column sections,
- wherein a defective one of the first normal column sections is configured to be substituted with one of the plurality of first redundant column sections, and
- wherein a defective one of the second normal column sections is configured to be substituted with one of the plurality of second redundant column sections.
3 more elements
An apparatus comprising:
- a first memory mat including a plurality of first column sections and a plurality of second column sections;
- and
- a second memory mat including a plurality of third column sections and a plurality of fourth column sections,
- wherein one of the plurality of first column sections or one of the plurality of third column sections is configured to be exclusively selected when a first bit of a column address is in a first logic level, and
- wherein both one of the plurality of second column sections and one of the plurality of fourth column sections are configured to be selected when the first bit of the column address is in a second logic level.
2 more elements
Dependencies are inferred from the claim text.