Time dependent dielectric breakdown reliability testing of a sram

A computer-implemented method of biasing a static random-access memory (SRAM) bit cell device of an SRAM memory modified for individual bit cell Time Dependent Dielectric Breakdown (TDDB) stress reliability testing, the method comprising:

• biasing an individual SRAM bit cell device via TDDB reliability testing;
• applying a plurality of stress voltages having different values that are higher than a predetermined maximum use voltage to the individual SRAM bit cell device;
• and
• recording a leakage current of the individual SRAM bit cell device undergoing the TDDB reliability testing and a time period of the recording,
• wherein the individual SRAM bit cell device comprises a pull up gate, a pull down gate, a pass gate, or a combination of a pass gate and a pull down gate.

A method of forming a semiconductor for individual reliability testing of a bit cell device in a static random-access memory (SRAM), the method comprising:

• providing a static random-access memory (SRAM) including a plurality of transistors;
• forming a first inverter and a second inverter cross-coupled to the first inverter from at least some of the plurality of transistors;
• providing a first access transistor and a second access transistor of the plurality of transistors configured to share a word line bias;
• connecting the second inverter and the second access transistor to have a shared first gate connection and to form respective bit cell devices each with two contacts;
• and
• configuring a second contact of each of the respective bit cell devices to be individually biased for reliability testing,
• wherein at least one contact of each of the respective bit cell devices comprises a floating diffusion contact.