Bitline voltage adjustment for program operation in a memory device

A system comprising:

• a memory device;
• and
• a processing device, operatively coupled to the memory device, the processing device to perform operations comprising:
• receiving a request to perform a program operation on a set of vertically stacked memory cells of a memory device, wherein each memory cell of the set of vertically stacked memory cells is addressable by a respective wordline;
• responsive to determining that at least one memory cell of the set of vertically stacked memory cells is non-programmable, determining, based on a number of program erase cycles (PECs) associated with the memory device, a bitline voltage adjustment value;
• adjusting a default bitline voltage by the bitline voltage adjustment value to generate an adjusted bitline voltage;
• and
• performing, using the adjusted bitline voltage, the program operation on the set of vertically stacked memory cells.