Semiconductor storage device and semiconductor storage device manufacturing method

A semiconductor storage device, comprising:

• a layered body including a plurality of gate electrode layers and a plurality of first insulating layers alternately stacked in a first direction;
• a first columnar body extending in the first direction;
• and
• a second columnar body extending in the first direction, wherein
• the gate electrode layers include a first gate electrode layer, and a second gate electrode layer that is disposed on a first side in the first direction with respect to the first gate electrode layer, and the second gate electrode layer has a length in a second direction that intersects the first direction less than a length of the first gate electrode layer in the second direction,
• the first gate electrode layer includes a terraced portion that does not coincide with the second gate electrode layer and a non-terraced portion that coincides with the second gate electrode layer,
• the first columnar body includes a first conductive portion that penetrates the terraced portion of the first gate electrode layer in the first direction and is electrically connected to the first gate electrode layer,
• the second columnar body includes a second conductive portion that penetrates the second gate electrode layer and the non-terraced portion of the first gate electrode layer in the first direction and is electrically connected to the second gate electrode layer, and an insulating portion disposed between the non-terraced portion of the first gate electrode layer and the second conductive portion, and
• a thickness in the first direction of the terraced portion and a thickness in the first direction of the non-terraced portion are identical to each other.

A semiconductor storage device manufacturing method, comprising:

• forming a layered body including a plurality of first sacrificial layers and a plurality of first insulating layers alternately stacked on top of one another in a first direction;
• forming a stepped region wherein respective lengths of the first sacrificial layers in a second direction that intersects the first direction differ from one another;
• etching the stepped region, and removing end portions of the first sacrificial layers, thereby forming a plurality of first space portions corresponding to the removed end portions of the first sacrificial layers;
• forming a plurality of holes that penetrate the first sacrificial layers in the first direction in the stepped region;
• etching through the holes, and removing one portion of the first sacrificial layers exposed by the holes, thereby forming a plurality of second space portions corresponding to the removed one portion of the first sacrificial layers;
• forming a plurality of insulating portions in the second space portions;
• replacing the first sacrificial layers with a plurality of conductive layers;
• and
• forming a plurality of conductive portions in the first space portions and the holes.