Integrated circuit device including an sram portion having end power select circuits

A method of operating an integrated circuit device including the steps of:

• enabling a power control circuit to provide power control signals according to at least one row address signal when an assist enable signal has an assist enable logic level and the integrated circuit device is in a write mode of operation, wherein data is written to at least one selected SRAM memory cell;
• selectively controlling at least one impedance path between a power supply potential and an array power line electrically connected to provide power to the at least one selected SRAM memory cell in a memory array in response to the at least one power control signal;
• providing a low impedance path between the power supply potential and the array power line on a first end of the memory array and providing a high impedance path between the power supply potential and the array power line on a second end of the memory array opposite to the first end of the memory array when the at least one selected SRAM memory cell is closer to the second end of the memory array;
• and
• providing a low impedance path between the power supply potential and the array power line on the second end of the memory array and providing a high impedance path between the power supply potential and the array power line on the first end of the memory array opposite to the second end of the memory array when the at least one selected SRAM memory cell is closer to the first end of the memory array;
• and
• providing the low impedance path between the power supply potential and the array power line on the first end of the memory array and the second end of the memory array when the assist enable signal has an assist disable logic level;
• wherein each at least one impedance path between the power supply potential and the array power line includes a plurality of channels between a source terminal and a drain terminal of an insulated gate field effect transistor (IGFET), the plurality of channels disposed in a first direction and substantially aligned in a second direction substantially perpendicular to the first direction and having a control gate structure that contiguously surrounds the plurality of channels.