Sram memory with random deterministic initialization

A memory device comprising a memory matrix arranged in rows and columns of SRAM memory cells, each column comprising a first bit line and a second complementary bit line respectively connected to access transistors of the memory cells of the column, each column being associated with an initialization circuit comprising a first coupling element and a second coupling element positioned respectively between, on the one hand, the first and second bit lines of the associated column and, on the other hand, a control block, the control unit being configured to impose a voltage on the bit lines when at least one of said coupling elements is rendered conductive in a deterministic initialization mode of all or some of the cells of the column, and wherein said control unit comprises at least one stage for drawing a random value, in order to generate a value or a logic state from two possible values or logic states ‘0’ or ‘1’ associated with a column, and wherein, in a so-called random deterministic initialization phase, the control unit successively controls for at least one selected column:

• the generation of a random value by said stage for drawing a random value associated with each selected column;
• then
• the activation of at least one coupling element from said first and second coupling elements of an initialization circuit associated with each selected column in order to connect at least one of the bit lines to the control unit which imposes a voltage value, the choice of said activated coupling element or the choice of the voltage value imposed being a function of the previously generated random value for the selected column, and the simultaneous activation of at least one access transistor of at least one cell of the selected column.