US 2024/0203484 A1Published application

Memory device

AssigneeKioxia Corporation

InventorKenya Tashiro

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Abstract

A first inverter circuit including second and third transistors coupled at a third node and a second inverter circuit including fourth and fifth transistors coupled at a fourth node are coupled between first and second nodes. An eighth transistor is coupled between a gate of the third transistor and the third node. A ninth transistor is coupled between a gate of the fifth transistor and the fourth node. A state in which first and second voltages are applied to the first and second nodes is formed at a first time. A third voltage is applied to the first node at a second time. A fourth voltage is applied to the second node at a third time. The second voltage is applied to the second node at a fourth time. The first voltage is applied to the first node at a fifth time.

Claims15

Dependent claims

A memory device comprising:

a capacitor;
a first transistor that has a first end coupled to the capacitor;
a first inverter circuit that is coupled between a first node and a second node and includes a p-type second transistor and an n-type third transistor coupled in series at a third node;
a second inverter circuit that is coupled between the first node and the second node and includes a p-type fourth transistor and an n-type fifth transistor coupled in series at a fourth node, the fifth transistor having a gate coupled to a second end of the first transistor;
a sixth transistor coupled between the gate of the fifth transistor and the third node;
a seventh transistor coupled between a gate of the third transistor and the fourth node;
an eighth transistor coupled between the gate of the third transistor and the third node;
and
a ninth transistor coupled between the gate of the fifth transistor and the fourth node, wherein
a state in which a first voltage is applied to the first node and a second voltage lower than the first voltage is applied to the second node is formed at a first time, a third voltage between the second voltage and the first voltage is applied to the first node at a second time after the first time, a fourth voltage between the second voltage and the first voltage is applied to the second node at a third time after the second time, the second voltage is applied to the second node at a fourth time after the third time, and the first voltage is applied to the first node at a fifth time after the fourth time.

7 more elements

A memory device comprising:

a capacitor;
a first transistor that has a first end coupled to the capacitor;
a first inverter circuit that is coupled between a first node and a second node and includes a p-type second transistor and an n-type third transistor coupled in series at a third node;
a second inverter circuit that is coupled between the first node and the second node and includes a p-type fourth transistor and an n-type fifth transistor coupled in series at a fourth node, the fifth transistor having a gate coupled to a second end of the first transistor;
a sixth transistor coupled between the gate of the fifth transistor and the third node;
a seventh transistor coupled between a gate of the third transistor and the fourth node;
an eighth transistor coupled between the gate of the third transistor and the third node;
a ninth transistor coupled between the gate of the fifth transistor and the fourth node;
a tenth transistor between a node of a first potential and the first node;
an eleventh transistor between the second node and a node of a second potential lower than the first potential;
and
a control circuit that
receives a first signal and a second signal,
includes a delay circuit that outputs a third signal that is a delayed version of the second signal,
applies a fourth signal having a level based on the first signal, the second signal, and the third signal to a gate of the eleventh transistor, and
applies a fifth signal having a level based on the first signal and the second signal to a gate of the tenth transistor.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/459,066Filed 31 Aug 2023
Priority: JP 2022-20338420 Dec 2022
Published: 20 Jun 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 11/4096
Read-write [R-W] circuits: input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G11C 11/4076
For memory cells of the field-effect type: timing circuits
G11C 11/4091
Read-write [R-W] circuits: sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or…
G11C 11/4094
Read-write [R-W] circuits: bit-line management or control circuits

Family

US 12,412,622 B2Related patent
US 2024/0203484 A1This patent

From the US filing history. Foreign family members aren’t listed.

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