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US 2024/0203483 A1Published application
Stacked semiconductor device
AssigneeRambus Inc.
InventorFrederick A. Ware
Life of this patent
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AssigneeRambus Inc.
InventorFrederick A. Ware
Estimating the term…
A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies.
(canceled)
An integrated circuit (IC) package, comprising:
A memory device, comprising:
A method of operation in a packaged semiconductor device, the packaged semiconductor device having a base die and a set of input/output (I/O) circuits formed in a corresponding set of integrated circuit (IC) memory die, the set of IC memory die stacked on the base die and coupled to the base die by through-silicon-via (TSV) circuitry, the method comprising:
Dependencies are inferred from the claim text.