Semiconductor memory device and memory system including the same

A memory system comprising:

• a memory controller configured to transmit a plurality of commands;
• and
• a memory device comprising:
• a memory cell array including a plurality of memory cell rows, each row including a plurality of memory cells;
• a control logic circuit configured to receive the plurality of commands from the memory controller and perform a memory operation in response to an active command and a first command among the plurality of commands;
• a row hammer management circuit configured to:
• count a number of accesses to a target memory cell row among the plurality of memory cell rows based on one or more active commands from the memory controller and store the number of accesses to the target memory cell row as first count data in the memory cell array,
• determine a hammer address based on a value of the first count data being greater than or equal to a reference value, and
• perform an internal read-update-write operation in response to a second command among the plurality of commands;
• and
• a refresh control circuit configured to receive the hammer address and perform refresh operation on one or more victim memory cell rows that are adjacent to the target memory cell row,
• wherein the first command is received after the active command, and the second command is received after a predetermined time from the first command.