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US 2024/0203469 A1Published application
Semiconductor apparatus including a plurality of clock paths and a semiconductor system using the same
AssigneeSK hynix Inc.
InventorJi Hyo KANG
Life of this patent
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Abstract
A semiconductor apparatus includes a plurality of clock paths, a first selecting circuit, and a multi-phase clock generating circuit. Each of the clock paths generates a corresponding clock signal pair according to an operation mode. The first selecting circuit outputs, as a reference clock signal pair, the corresponding clock signal pair. The multi-phase clock generating circuit generates first internal clock signals based on the reference clock signal pair.
Claims23
A semiconductor apparatus including a plurality of clock paths, the semiconductor apparatus comprising:
- a first clock path configured to buffer a system clock signal pair to generate a first clock signal pair in a first operation mode;
- a second clock path configured to multiply a frequency of the system clock signal pair to generate a second clock signal pair in a second operation mode;
- a third clock path configured to convert the system clock signal pair to a Complementary Metal-Oxide-Semiconductor (CMOS) level to generate a third clock signal pair in a third operation mode;
- a first selecting circuit configured to output, as a first reference clock signal pair, one of the first clock signal pair, the second clock signal pair, and the third clock signal pair according to the operation mode;
- and
- a multi-phase clock generating circuit configured to generate first internal clock signals from the first reference clock signal pair.
3 more elements
A semiconductor apparatus including a plurality of clock paths, the semiconductor apparatus comprising:
- a first clock path configured to buffer a system clock signal pair to generate a first clock signal pair in a first operation mode;
- a second clock path configured to multiply a frequency of the system clock signal pair to generate a second clock signal pair in a second operation mode;
- a third clock path configured to convert the system clock signal pair to a Complementary Metal-Oxide-Semiconductor (CMOS) level to generate a third clock signal pair and configured to buffer the system clock signal pair to a Current Mode Logic (CML) level to generate a fourth clock signal pair, in a third operation mode;
- a first selecting circuit configured to select, as a first reference clock signal pair, one of the first clock signal pair, the second clock signal pair, and the third clock signal pair according to the operation mode;
- a multi-phase clock generating circuit configured to generate first internal clock signals, second internal clock signals, and a second reference clock signal pair from the first reference clock signal pair;
- and
- a second selecting circuit configured to select, according to the operation mode, at least one of the second reference clock signal pair and the fourth clock signal pair to output the selected pair as a third internal clock signal pair.
4 more elements
A semiconductor apparatus including a plurality of clock paths, the semiconductor apparatus comprising:
- a first clock path configured to buffer a system clock signal pair to generate a first clock signal pair in a first operation mode;
- a second clock path configured to multiply a frequency of the system clock signal pair to generate a second clock signal pair in a second operation mode;
- a third clock path configured to convert the system clock signal pair to a Complementary Metal-Oxide-Semiconductor (CMOS) level to generate a third clock signal pair and configured to buffer the system clock signal pair to a Current Mode Logic (CML) level to generate a fourth clock signal pair, in a third operation mode;
- a first selecting circuit configured to selecting, as a first reference clock signal pair, one of the first clock signal pair, the second clock signal pair, and the third clock signal pair according to the operation mode;
- a multi-phase clock generating circuit configured to generate first internal clock signals, second internal clock signals, and a second reference clock signal pair based on at least one of a third internal clock signal pair and the first reference clock signal pair;
- and
- a second selecting circuit configured to select one of the second reference clock signal pair and the fourth clock signal pair to output the selected pair as the third internal clock signal pair.
4 more elements
Dependencies are inferred from the claim text.