Shift register unit and driving method therefor, gate drive circuit, and display device

A gate drive circuit, comprising at least two cascaded shift register units;

• wherein
• the shift register unit comprises:
• a first input circuit coupled to a first clock terminal, a first node, a second node, a third node, a pull-up power supply terminal, and a pull-down power supply terminal, wherein first input circuit is configured to control the pull-up power supply terminal to be conducted or non-conducted with the first node and control the pull-down power supply terminal to be conducted or non-conducted with the first node in response to a first clock signal provided by the first clock terminal;
• and control the pull-up power supply terminal to be conducted or non-conducted with the third node and control the pull-down power supply terminal to be conducted or non-conducted with the third node in response to a potential of the second node;
• a second input circuit coupled to the first node, the second node, the third node, the pull-up power supply terminal, the pull-down power supply terminal, an input control terminal, and the first clock terminal, wherein second input circuit is configured to control the pull-up power supply terminal to be conducted or non-conducted with the second node and control the pull-down power supply terminal to be conducted or non-conducted with the second node in response to a potential of the first node, a potential of the third node, the first clock signal, and an input control signal provided by the input control terminal;
• and
• an output circuit coupled to the pull-up power supply terminal, the pull-down power supply terminal, the third node, a second clock terminal, and an output terminal, wherein output circuit is configured to control the pull-up power supply terminal to be conducted or non-conducted with the output terminal and control the pull-down power supply terminal to be conducted or non-conducted with the output terminal in response to the potential of the third node and a second clock signal provided by the second clock terminal;
• and
• the gate drive circuit comprises:
• the first clock terminal of the shift register unit at an odd-numbered stage is coupled to a first clock signal line and the second clock terminal of the shift register unit at the odd-numbered stage is coupled to a second clock signal line;
• and
• the first clock terminal of the shift register unit at an even-numbered stage is coupled to the second clock signal line and the second clock terminal of the shift register unit at the even-numbered stage is coupled to the first clock signal line.

A display device, comprising a display panel and the gate drive circuit;

• wherein
• the gate drive circuit comprises at least two cascaded shift register units, wherein
• the shift register unit comprises:
• a first input circuit coupled to a first clock terminal, a first node, a second node, a third node, a pull-up power supply terminal, and a pull-down power supply terminal, wherein first input circuit is configured to control the pull-up power supply terminal to be conducted or non-conducted with the first node and control the pull-down power supply terminal to be conducted or non-conducted with the first node in response to a first clock signal provided by the first clock terminal;
• and control the pull-up power supply terminal to be conducted or non-conducted with the third node and control the pull-down power supply terminal to be conducted or non-conducted with the third node in response to a potential of the second node;
• a second input circuit coupled to the first node, the second node, the third node, the pull-up power supply terminal, the pull-down power supply terminal, an input control terminal, and the first clock terminal, wherein second input circuit is configured to control the pull-up power supply terminal to be conducted or non-conducted with the second node and control the pull-down power supply terminal to be conducted or non-conducted with the second node in response to a potential of the first node, a potential of the third node, the first clock signal, and an input control signal provided by the input control terminal;
• and
• an output circuit coupled to the pull-up power supply terminal, the pull-down power supply terminal, the third node, a second clock terminal, and an output terminal, wherein output circuit is configured to control the pull-up power supply terminal to be conducted or non-conducted with the output terminal and control the pull-down power supply terminal to be conducted or non-conducted with the output terminal in response to the potential of the third node and a second clock signal provided by the second clock terminal;
• the display panel comprises a plurality of pixel circuits;
• and
• the gate drive circuit is coupled to gate signal terminals in the pixel circuits, and is configured to provide gate drive signals to the gate signal terminals.