Acceleration of 2d dilated convolution for efficient analytics

A system comprising:

• a hardware accelerator including:
• an input feature panel memory,
• a convolutional result memory, and
• a filter vector memory;
• a controller;
• and
• a memory having stored thereon instructions that, upon execution by the controller, cause the controller to:
• receive an input feature map,
• determine an offset based on a dilation factor,
• implement a loading plan to carry out more than one phase of 2-dimensional (2D) dilated convolution based on the dilation factor, each phase including:
• applying a dilated filter to the input feature map to load values into the input feature panel memory nonsequentially based on the offset for a convolution iteration;
• and
• instructing the hardware accelerator to perform the convolution iteration, and
• implement an output plan including:
• retrieving values from the convolutional result memory on completion of the convolution iteration;
• and
• storing the values in a row of a convolution result matrix based on the offset.

A method of executing dilated convolution, comprising:

• receiving, by a controller, an input feature map;
• executing a phase of a number of phases of dilated convolution of the input feature map, wherein the number of phases is based on a dilation factor of the dilated convolution, and wherein the executing the phase comprises:
• selecting, by the controller, a starting row of the input feature map for the phase,
• convolving an input feature panel with a filter vector wherein the convolving comprises:
• applying, by the controller, a dilated filter to the input feature map, wherein the dilated filter comprises a set of filter coefficients separated by the dilation factor;
• loading, by the controller, a set of values into an input feature panel based on applying the dilated filter to a set of rows of the input feature map to implement vertical reuse;
• accessing, by a convolution processor, the filter vector comprising the set of filter coefficients;
• convolving, by the convolution processor, the filter vector with the input feature panel to generate an output;
• assigning, by the controller, the output to a selected row of a convolution result matrix wherein the selected row is selected based on the dilation factor and the phase;
• and
• shifting, by the controller, the dilated filter down the input feature map based on the dilation factor, and
• repeating the convolving until the dilated filter has been shifted to an end of the input feature map;
• and
• repeating the executing the phase for each phase of the number of phases.