High Density Transistor and Routing Track Architecture

A device comprising:

• a first cell comprising a first transistor having a first gate and a second transistor having a second gate, the first gate and the second gate arranged along a gate line extending in a first direction;
• a second cell comprising a third transistor having a third gate and a fourth transistor having a fourth gate, the third gate and the fourth gate arranged along the gate line;
• and
• a metal layer over the first cell and the second cell, the metal layer comprising a plurality of routing tracks arranged at a first pitch, each routing track extending in a second direction perpendicular to the first direction, and the plurality of routing tracks comprising:
• a first routing track over the first gate;
• a second routing track over the second gate;
• and
• a third routing track between and adjacent to the first routing track and the second routing track.

A method for forming a device, the method comprising:

• forming a first transistor comprising a portion of a first diffusion region of a first type, the first diffusion region extending in a first direction;
• forming a second transistor comprising a portion of a second diffusion region of a second type, the second diffusion region extending in the first direction;
• forming a first metal line over the first transistor;
• forming a second metal line over the second transistor;
• and
• forming a third metal line in a same layer as the first metal line and the second metal line, the third metal line adjacent to the first metal line and the second metal line, the third metal line not over the first transistor or the second transistor.