Secure semiconductor and system design

A secure semiconductor device, comprising:

• a network on chip (NoC) module;
• an electronic field-programmable gate array (eFPGA) configuration module;
• and
• a clock operatively coupled to the eFPGA configuration module via the NoC module, the clock configured to assert a RESET signal in response to an absence of FPGA configuration data stored in the eFPGA configuration module, thereby disabling operation of the device.

A secure system, comprising:

• a data port;
• a network on chip (NoC) module;
• a processor communicatively coupled to the NoC module;
• a communication interface operatively coupled to the processor and to the data port;
• an electronic field-programmable gate array (eFPGA) configuration module operatively coupled to the NoC module;
• and
• a clock operatively coupled to the NoC module;
• wherein in a first modality, the communication interface is at least partially disabled;
• wherein in a second modality, the communication interface is at least partially disabled, boundary scan operations are disabled, a RESET signal is held in a constant state, and/or redacted code is rendered inoperable;
• and
• wherein in a third modality, the communication interface is at least partially enabled to send and receive commands and data via the data port, the boundary scan operations are enabled, the RESET signal is not held in the constant state, and/or the redacted code is operable.