Memory device for performing target refresh operation, and operation method thereof

An operation method of a memory device, comprising:

• generating a first aggressive address by latching an address input with a refresh management command, and sequentially storing the first aggressive address as a plurality of first candidate addresses;
• generating a second aggressive address by collecting information on rows subjected to a row-hammer attack;
• refreshing, according to the refresh management command, one or more rows regarding the first aggressive address;
• and
• refreshing one or more rows regarding the second aggressive address when a number of duplicated addresses becomes m or more, among the plurality of the first candidate addresses while the refresh management command is input k times, where k is a natural number and m is a natural number less than or equal to k.

A memory device, comprising:

• a refresh latch configured to generate a first aggressive address by latching an address input with a refresh management command;
• a detection circuit configured to generate a detection signal according to a number of inputs of the refresh management command;
• an address sampling circuit configured to generate a second aggressive address by collecting information on rows subjected to a row-hammer attack;
• and
• an output control circuit configured to output, as a target address, the first aggressive address or the second aggressive address according to the refresh management command and the detection signal.

An operation method of a memory device, comprising:

• generating a first aggressive address by latching an address input with a refresh management command;
• generating a second aggressive address by collecting information on rows subjected to a row-hammer attack;
• refreshing, according to the refresh management command, one or more rows regarding the first aggressive address;
• and
• refreshing one or more rows regarding the second aggressive address when a number of inputs of the refresh management command reaches a threshold.

A memory device, comprising:

• a refresh latch configured to generate a first aggressive address by latching an address input with a refresh management command;
• a detection circuit configured to:
• determine, according to refresh rate information, whether to activate an additional refresh signal when the refresh management command is input, and
• generate a detection signal when the refresh management command is input and the additional refresh signal is determined to be deactivated;
• an address sampling circuit configured to generate a second aggressive address by collecting information on rows subjected to a row-hammer attack;
• and
• an output control circuit configured to output, as a target address, the first aggressive address or the second aggressive address according to the refresh management command and the detection signal.

An operation method of a memory device, comprising:

• generating a first aggressive address by latching an address input with a refresh management command;
• generating a second aggressive address by collecting information on rows subjected to a row-hammer attack;
• refreshing, according to the refresh management command, one or more first adjacent rows of a first target row corresponding to the first aggressive address;
• and
• refreshing, according to the refresh management command, one or more adjacent rows of a second target row corresponding to the second aggressive address when it is determined that refreshing for second adjacent rows of the first target row is omitted according to refresh rate information.