Two-transistor chip and three-transistor chip identification bit cells

A semiconductor bit cell, comprising:

• a first transistor comprising a first gate dielectric located between a first gate electrode and a first channel region, wherein a first source is located on a first side of the first channel region and a first drain is located on a second side of the first channel region, the first gate dielectric has a first thickness between the first gate electrode and the first channel region substrate, and
• a second transistor comprising a second gate dielectric located between a second gate electrode and a second channel region, wherein a second source is located on a first side of the second channel region and a second drain is located on a second side of the second channel region, the second gate electrode is electrically connected to the first transistor via the first drain, the second gate dielectric has a second thickness between the second gate electrode and the second channel drain, the second thickness is less than the first thickness, wherein, in the event of a breakdown voltage is applied to the second transistor, the second gate dielectric is configured to irreversibly breakdown prior to breakdown of the first gate dielectric.

A method for creating an identification code for a semiconductor device:

• fabricating a bit cell located on the semiconductor device, wherein the bit cell comprises a first transistor including a first gate dielectric having a first thickness and a second transistor including a second gate dielectric having a second thickness, wherein the first thickness is greater than the second thickness and the first transistor is electrically connected to the second transistor;
• and
• applying a voltage to the first transistor wherein the voltage has a magnitude sufficient to cause breakdown of the second gate dielectric and insufficient to cause breakdown of the first gate dielectric.