Memory Device Bandwidth Optimization

A method, comprising:

• receiving, by a memory circuit over a first plurality of command bus cycles, a particular series of commands for accessing a plurality of memory banks in the memory circuit, including:
• receiving a set of activation commands for a particular memory bank of the plurality of memory banks;
• receiving, after a particular number of command bus cycles from receiving the set of activation commands, a sync command;
• and
• based at least on an indication of a sync delay mode, activating a data bus clock signal after a delay of one or more command bus cycles from receiving the sync command.

An apparatus, comprising:

• a memory interface circuit configured to couple to a memory device via a command bus including a command clock signal and a data bus including a data clock signal, wherein the memory device includes a plurality of memory banks;
• and
• a control circuit coupled to the memory interface circuit and configured to:
• send a set of activate commands that indicate a particular memory bank of the memory device;
• send, a number of command clock cycles after the last of the set of activation commands is sent, a sync command that causes the memory device to start the data clock signal;
• and
• send, after a determined number of command clock cycles, a read command for the particular memory bank.