Concurrent Support for Multiple Cache Inclusivity Schemes Using Low Priority Evict Operations

A method comprising:

• receiving a first eviction message having a lower priority than probe messages from a first inner cache;
• receiving a second eviction message having a higher priority than probe messages from a second inner cache;
• transmitting a third eviction message, determined based on the first eviction message, having the lower priority than probe messages to a circuitry that is closer to memory in a cache hierarchy;
• and
• transmitting a fourth eviction message, determined based on the second eviction message, having the lower priority than probe messages to the circuitry that is closer to memory in the cache hierarchy.

A non-transitory computer readable medium comprising a circuit representation that, when processed by a computer, is used to program or manufacture an integrated circuit comprising:

• a first inner cache that is configured to transmit eviction messages having a lower priority than probe messages;
• a second inner cache that is configured to transmit eviction messages having a higher priority than probe messages;
• and
• a shared cache that is connected to the first inner cache and to the second inner cache as parts of a cache hierarchy, and configured to:
• receive a first eviction message having the lower priority than probe messages from the first inner cache;
• receive a second eviction message having the higher priority than probe messages from the second inner cache;
• transmit a third eviction message, determined based on the first eviction message, having the lower priority than probe messages to a circuitry that is closer to memory in the cache hierarchy;
• and
• transmit a fourth eviction message, determined based on the second eviction message, having the lower priority than probe messages to the circuitry that is closer to memory in the cache hierarchy.