US 2024/0202131 A1 · PROCESSOR-BASED SYSTEM FOR ALLOCATING CACHE LINES TO A HIGHER-LEVEL CACHE MEMORY

Abstract

A processor-based system for allocating a higher-level cache line in a higher-level cache memory in response to an eviction request of a lower-level cache line is disclosed. The processor-based system determines whether the cache line is opportunistic, sets an opportunistic indicator to indicate that the lower-level cache line is opportunistic, and communicates the lower-level cache line and the opportunistic indicator. The processor-based system determines, based on the opportunistic indicator of the lower-level cache line, whether a higher-level cache line of a plurality of higher-level cache lines in the higher-level cache memory has less or equal importance than the lower-level cache line. In response, the processor-based system replaces the higher-level cache line in the higher-level cache memory with the lower-level cache line and associates the opportunistic indicator with the lower-level cache line in the higher-level cache memory.

Claims22

Dependent claims

A processor-based system for allocating a cache line to a higher-level cache memory, comprising:

a lower-level cache memory configured to store data;
the processor-based system configured to, in response to an eviction request of a lower-level cache line in the lower-level cache memory:
determine whether the lower-level cache line is opportunistic;
set an opportunistic indicator to indicate whether the lower-level cache line is opportunistic;
communicate the lower-level cache line and the opportunistic indicator indicating that the lower-level cache line is opportunistic to the higher-level cache memory;
determine, based on the opportunistic indicator of the lower-level cache line, whether a higher-level cache line of a plurality of higher-level cache lines in the higher-level cache memory has less or equal importance than the lower-level cache line;
and
in response to the determining the higher-level cache line has less or equal importance than the lower-level cache line:
replace the higher-level cache line in the higher-level cache memory with the lower-level cache line;
and
associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

8 more elements

A method for allocating a cache line to a higher-level cache memory in response to an eviction request of a lower-level cache line in a lower-level cache memory, comprising:

determining whether the lower-level cache line is opportunistic;
setting an opportunistic indicator to indicate whether the lower-level cache line is opportunistic;
communicating the lower-level cache line and the opportunistic indicator indicating that the lower-level cache line is opportunistic to the higher-level cache memory;
determining, based on the opportunistic indicator of the lower-level cache line, whether a higher-level cache line of a plurality of higher-level cache lines in the higher-level cache memory has less or equal importance than the lower-level cache line;
and
in response to the determining the higher-level cache line has less or equal importance than the lower-level cache line:
replacing the higher-level cache line in the higher-level cache memory with the lower-level cache line;
and
associating the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

6 more elements

Dependencies are inferred from the claim text.

Processor-based system for allocating cache lines to a higher-level cache memory

Life of this patent

Processor-based system for allocating cache lines to a higher-level cache memory

Life of this patent

Abstract

Claims22