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US 2024/0202125 A1Published application
Coherency bypass tagging for read-shared data
AssigneeIntel Corporation
InventorsNeha Gholkar, Akhilesh Kumar
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Abstract
An example of an apparatus may include memory, two or more caches, and circuitry coupled to the memory and the two or more caches to selectively maintain coherency of data shared among the memory and the two or more caches based on coherency bypass information associated with the data. Other examples are disclosed and claimed.
Claims20
An apparatus, comprising:
- a processor coupled to at least a first cache and a second cache;
- and
- circuitry coupled to the first and second caches to selectively maintain coherency of data shared among a memory and the first and second caches based on coherency bypass information associated with the data.
An apparatus comprising:
- decoder circuitry to decode a single instruction, the single instruction to include a field for an identifier of a first source operand and a field for an opcode, the opcode to indicate execution circuitry is to update coherency bypass information;
- and
- execution circuitry to execute the decoded instruction according to the opcode to update coherency bypass information for data indicated by the first source operand.
A method, comprising:
- fetching an instruction having a field for an opcode and a field for an identifier of a first source operand;
- decoding the instruction;
- scheduling execution of the instruction;
- and
- executing the decoded instruction according to the opcode to update coherency bypass information for data indicated by the first source operand.
2 more elements
Dependencies are inferred from the claim text.