Peripheral component interconnect board programmable link training and status state machine and state branching

A device, comprising:

• one or more memories;
• and
• one or more processors, coupled to the one or more memories, configured to:
• generate a link training and status state machine (LTSSM) test configuration that includes states and paths connecting the states;
• provide the LTSSM test configuration for tracing through by a device under test,
• wherein the device under test is an endpoint device or a root complex device;
• receive results associated with tracing through of the LTSSM test configuration by the device under test;
• modify, based on the results, one of the paths of the LTSSM test configuration to include a different one of the states and to generate a modified LTSSM test configuration;
• and
• provide the modified LTSSM test configuration for tracing through by the device under test.

A non-transitory computer-readable medium storing a set of instructions, the set of instructions comprising:

• one or more instructions that, when executed by one or more processors of a device, cause the device to:
• generate a link training and status state machine (LTSSM) test configuration that includes states and paths connecting the states;
• provide the LTSSM test configuration for tracing through by a device under test;
• receive results associated with tracing through of the LTSSM test configuration by the device under test;
• modify, based on the results, the LTSSM test configuration to generate a modified LTSSM test configuration;
• and
• provide the modified LTSSM test configuration for tracing through by the device under test.