Routing raw debug data using trace infrastructure in processor-based devices

A processor-based device, comprising:

• means for receiving raw debug data from a subsystem circuit of the processor-based device;
• means for generating a debug trace packet comprising the raw debug data in lieu of formatted trace data;
• and
• means for transmitting, via a trace interconnect bus of the processor-based device, the debug trace packet comprising the raw debug data to an I/O endpoint circuit of the processor-based device during a period of trace interconnect bus inactivity.

A method for routing raw debug data using trace infrastructure, comprising:

• receiving, by a debug transmit circuit of a subsystem circuit of a processor-based device, raw debug data from the subsystem circuit;
• generating, by the debug transmit circuit, a debug trace packet comprising the raw debug data in lieu of formatted trace data;
• and
• transmitting, by the debug transmit circuit via a trace interconnect bus of the processor-based device, the debug trace packet comprising the raw debug data to an input/output (I/O) endpoint circuit of the processor-based device during a period of trace interconnect bus inactivity.