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US 2024/0202073 A1Published application
Read recovery
AssigneeMicron Technology, Inc.
InventorsPrashant Parashari, Gaurav Singh
Life of this patent
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Abstract
A sign bit of a low-density parity-check (LDPC) codeword associated with a translation unit (TU) can be generated by performing an XOR operation on a RAIN drop corresponding to the TU and a raw read of the TU. The LDPC codeword can include a hard bit and three soft bits that include the sign bit. The LDPC codeword can be decoded using the hard bit and the three soft bits. A read recovery operation can be performed on the TU using the decoded LDPC codeword.
Claims20
An apparatus, comprising:
- a memory configured to store a number of redundant array of independent NAND (RAIN) stripes each comprising a plurality of translation units (TUs);
- and
- read recovery circuitry configured to, responsive to identifying a failed TU corresponding to a particular one of the number of RAIN stripes:
- generate a sign bit of for a low-density parity-check (LDPC) decoding operation by:
- determining a rain drop corresponding to the particular rain stripe;
- performing a raw read of the failed TU;
- and
- performing an exclusive OR (XOR) operation the rain drop and the raw read of the failed TU;
- and
- perform the LDPC decoding operation utilizing the generated sign bit as a soft bit in addition to at least two other soft bits and a hard bit.
7 more elements
A method, comprising:
- storing, in a memory, a hard bit, a first soft bit, and a second soft bit associated with a translation unit (TU), wherein the TU is one of a plurality of TUs corresponding to a redundant array of independent NAND (RAIN) stripes;
- and
- storing, in the RAIN stripe, a parity value corresponding to an exclusive OR (XOR) of all of the TUs corresponding to the RAIN stripe;
- and
- responsive to a number of unsuccessful attempts to recover a determined failure of the TU:
- generating a sign bit of for a low-density parity-check (LDPC) decoding operation by:
- performing a raw read of the failed TU;
- and
- performing an XOR operation the parity value and the raw read of the failed TU;
- and
- performing the LDPC decoding operation utilizing the generated sign bit as a soft bit in addition to the hard bit, the first soft bit, and the second soft bit.
8 more elements
An apparatus, comprising:
- a memory configured to store a number of redundant array of independent NAND (RAIN) stripes each comprising a plurality of translation units (TUs);
- and
- control circuitry configured to, responsive to a read operation performed on a particular TU resulting in a determined number of errors, execute an error handling flow comprising:
- performing a number of read retry operations on the TU;
- responsive to the number of read retry operations failing to recover the TU, and prior to attempting a RAIN recovery operation:
- generating a sign bit by performing an exclusive OR (XOR) operation between a raw read of the TU and a parity value corresponding to a RAIN stripe that includes the TU, wherein the parity value is written along with the RAIN stripe and is an XORed value of the TUs corresponding to the RAIN stripe;
- and
- performing a low density parity check (LDPC) decode operation to attempt to recover the TU by utilizing the generated sign bit as a soft bit in addition to at least two other soft bits and a hard bit.
5 more elements
Dependencies are inferred from the claim text.