US 2024/0202038 A1 · HARDWARE INTEGRATED, PRIORITY-ENCODED DOMAINS

Abstract

Systems and methods for priority encoded domains in an SoC have been described. In an illustrative, non-limiting embodiment, a processing system in an SoC, may include: a core, and a domain access controller coupled to the core. The domain access controller may be configured to: receive a resource transaction request from a master device associated with a software-defined processing domain, and process the resource transaction request based upon a priority level of the software-defined processing domain. The domain access controller may also order a plurality of resource transaction requests based upon the associated respective priority levels, and provide the resource transaction requests to resources based on the order. A hypervisor can also use the priority levels of the software-defined processing domains to allocate a plurality of virtual machines to a plurality of processing cores according to the priority levels.

Claims20

Dependent claims

A System-on-Chip (SoC), comprising:

a core;
and
a domain access controller coupled to the core, wherein the domain access controller is configured to:
receive a resource transaction request from a master device associated with a software-defined processing domain;
and
process the resource transaction request, at least in part, based upon a priority level of the software-defined processing domain.

3 more elements

A method, comprising:

receiving, at a domain access controller, a plurality of resource transactions issued by a plurality of master devices, wherein each of the plurality of master devices is associated with a respective one of a plurality of software-defined processing domains, and wherein each of the plurality of software-defined processing domains is associated with a priority attribute;
re-ordering the plurality of resource transactions, by the domain access controller, based upon the priority attributes;
and
executing the re-ordered resource transactions.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

18/067,446Filed 16 Dec 2022

Published

20 Jun 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification14 codes

G06F 9/5038
The resource being a machine, e.g. CPUs, Servers, Terminals: considering the execution order of a plurality of tasks, e.g. taking priority or time…
G06F 9/45558
Hypervisors; Virtual machine monitors: hypervisor-specific management and integration aspects
G06F 9/5027
To service a request: the resource being a machine, e.g. CPUs, Servers, Terminals
G06F 12/1441
The protection being physical, e.g. cell, word, block: for a range

Hardware integrated, priority-encoded domains

Life of this patent

Hardware integrated, priority-encoded domains

Life of this patent

Abstract

Claims20