Accessing Multiple Physical Partitions of a Hardware Device

Abstract

In a computing device, a hardware device (e.g., a parallel accelerated processor or graphics processing unit) is coupled to a bus, such as a peripheral component interconnect express (PCIe) bus. The hardware device supports physical partitioning that allows physical resources of the hardware device to be separated into different partitions. Examples of such physical resources include engine resources (e.g., compute resources, direct memory access resources), memory resources (e.g., random access memory), and so forth. Each physical partition is mapped to a physical function that is exposed to a host on the computing device in a manner that is compliant with the bus protocol, allowing software to access the physical partition in a conventional manner based on the bus protocol.

Dependencies are inferred from the claim text.